1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for suppressing a short-circuit current in a memory cell array where a cross failure, that is a short circuit of a world line and bit line, occurred.
2. Description of the Related Art
A semiconductor memory device, particularly a DRAM which has a large capacity, has a redundant cell array to avoid a drop in yield due to defective bits. A column or a row where a defective bit is detected in the operation test is replaced with a redundant cell array. As a result, a column or row having a defective bit is not selected.
One failure is the short-circuiting of a word line and bit line (cross failure). In a cell array having a cross failure, short-circuit current is generated in the standby state (precharge state) even if the cell array is not selected. In other words, in the standby status, all the word lines are driven to the L level (Vss or negative potential), and the bit lines are precharged to a precharge level, Vcc/2 or Vii/2 (Vii is an internal cell power supply). Therefore if a cross failure occurs in the precharge state, short-circuit current is generated from a bit line in the precharge state to a word line in L level.
Japanese Patent Application Laid-Open No. H9-69300 states that in order to prevent short-circuit current due to a cross failure, a transistor is formed between a precharge circuit and a precharge power supply for supplying precharge voltage to a pair of bit lines, and this transistor is controlled to the OFF state in a failure column so as to prevent the short-circuit current.
Japanese Patent Application Laid-open No. H11-149793 states that in order to prevent short-circuit current due to a cross failure, a transistor, as a current limiting element, is formed not only in a precharge power supply line of the precharge circuit of a bit line, but also in a precharge power supply line of a precharge circuit of a drive signal line for driving a sense amplifier, and this current limiting element is set to OFF by a column select signal. According to this patent document, a transistor for current limiting is created in a precharge circuit of a drive signal line of a sense amplifier, which is commonly formed for a plurality of bit line pairs.
Also Japanese Patent Application Laid-Open No. H4-34200 states that the control signal of a load circuit of a failure bit line is set to L level so that the load current does not flow in the SRAM. In this patent document, however, the prevention of a short-circuit current due to the cross failure of a DRAM is not stated.
According to Japanese Patent Application Laid-Open No. H11-149793, a transistor for interrupting the short-circuit current is formed between a precharge circuit of a bit line pair and a precharge power supply, and also a transistor for interrupting the short-circuit current is formed between a precharge circuit of a sense amplifier drive signal line and a precharge power supply.